IEEE SCV-Photonics Chapter Technical Meeting on August 4

6:00pm: Networking/Pizza Social
7:00pm: Presentation
8:00pm: Adjourn

Cost: Free


Advanced lithography techniques for 22nm half-pitch and beyond


Dr. Yashesh A. Shroff, Intel


Immersion lithography has become the mainstay of 45nm and below half-pitch nodes, having overcome a number of challenges on the way to high volume manufacturing. Significantly, extensions to immersion such as double-exposure and double patterning have shown capability to reach up to 22nm HP node and perhaps even lower. In this talk, I will focus on providing an overview of double-patterning techniques, modeling results, overlay challenge, cost, and computational lithography approaches. A brief comparison with other exciting competing patterning technologies such as EUV and nano-imprint will be provided to help set baseline.


Yashesh A. Shroff completed his BS in EE from UT Austin in '97 and MS/PhD from UC Berkeley in '99 and 2003 respectively. His main area of interest is maskless lithography based on a variety of direct write technologies such as modulating large micromirror arrays. Since 2003, Yashesh has been a litho engineer at Intel Corp where he is involved in the development of next generation lithography. His current focus is on immersion double patterning techniques and moving EUV lithography towards a high volume manufacturing platform.

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